EP2SGX30CF780C5N Datasheet, PDF (217/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

DC and Switching Characteristics
Table 4–29. 2.5-V LVDS I/O Specifications
Symbol
Parameter
Conditions
V_CCIO
I/O supply voltage for left and
right I/O banks (1, 2, 5, and
6)
V_ID
Input differential voltage
swing (single-ended)
V_ICM
V_OD
V_OCM
R_L
Input common mode voltage
Output differential voltage
(single-ended)
R_L = 100 Ω
Output common mode
voltage
R_L = 100 Ω
Receiver differential input
discrete resistor (external to
Stratix II GX devices)
Minimum
2.375
Typical
2.5
Maximum Unit
2.625
V
100
200
250
1.125
90
350
1,250
100
900
mV
1,800 mV
450
mV
1.375
V
110
Ω
Table 4–30. 3.3-V LVDS I/O Specifications
Symbol
Parameter
Conditions
V_CCIO (1)
I/O supply voltage for top and
bottom PLL banks (9, 10, 11,
and 12)
V_ID
Input differential voltage
swing (single-ended)
V_ICM
V_OD
V_OCM
Input common mode voltage
Output differential voltage
(single-ended)
R_L = 100 Ω
Output common mode
voltage
R_L = 100 Ω
R_L
Receiver differential input
discrete resistor (external to
Stratix II GX devices)
Minimum
3.135
Typical
3.3
Maximum Unit
3.465
V
100
350
900
mV
200
1,250
1,800 mV
250
710
mV
840
1,570 mV
90
100
110
Ω
Note to Table 4–30:
(1) The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by V_CCINT, not V_CCIO.
The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock
output/feedback operation, connect VCC_PLL_OUT to 3.3 V.
Altera Corporation
June 2009
4–47
Stratix II GX Device Handbook, Volume 1