EP2SGX30CF780C5N Datasheet, PDF (236/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Timing Model
Table 4–55 shows the Stratix II GX performance for some common
designs. All performance values were obtained with the Quartus II
software compilation of LPM or MegaCore functions for FIR and FFT
designs.
Table 4–55. Stratix II GX Performance Notes (Part 1 of 3) Note (1)
Resources Used
Performance
Applications
LE
16-to-1
multiplexer (4)
32-to-1
multiplexer (4)
16-bit counter
64-bit counter
TriMatrix
Memory
M512
block
Simple
dual-port RAM
32 x 18bit
FIFO 32 x 18 bit
TriMatrix Simple dual-
Memory port RAM 128 x
M4K block 36bit
True dual-port
RAM 128 x 18bit
FIFO 128 x 36
bit
ALUTs
21
38
16
64
0
22
0
0
22
TriMatrix
Memory
Blocks
DSP
Blocks
-3 Speed
Grade
(2)
0
0
657.03
0
0
534.75
0
0
568.18
0
0
242.54
1
0
500.0
1
0
500.00
1
0
540.54
1
0
540.54
1
0
524.10
-3
Speed
Grade
(3)
-4 Speed
Grade
620.73 589.62
517.33 472.81
539.66
231.0
476.19
507.61
217.77
447.22
476.19
515.46
460.82
483.09
515.46 483.09
500.25 466.41
-5
Speed Units
Grade
477.09 MHz
369.27 MHz
422.47
180.31
373.13
MHz
MHz
MHz
373.13 MHz
401.6 MHz
401.6 MHz
381.38 MHz
4–66
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009