EP2SGX30CF780C5N Datasheet, PDF (168/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Automated Single Event Upset (SEU) Detection
The temperature sensing diode is a very sensitive circuit which can be
influenced by noise coupled from other traces on the board, and possibly
within the device package itself, depending on device usage. The
interfacing device registers temperature based on millivolts of difference
as seen at the TSD. Switching I/O near the TSD pins can affect the
temperature reading. Altera recommends you take temperature readings
during periods of no activity in the device (for example, standby mode
where no clocks are toggling in the device), such as when the nearby I/Os
are at a DC state, and disable clock networks in the device.
Automated
Single Event
Upset (SEU)
Detection
Stratix II GX devices offer on-chip circuitry for automated checking of
single event upset (SEU) detection. Some applications that require the
device to operate error free at high elevations or in close proximity to
Earth’s North or South Pole will require periodic checks to ensure
continued data integrity. The error detection cyclic redundancy check
(CRC) feature controlled by the Device & Pin Options dialog box in the
Quartus II software uses a 32-bit CRC circuit to ensure data reliability and
is one of the best options for mitigating SEU.
You can implement the error detection CRC feature with existing circuitry
in Stratix II GX devices, eliminating the need for external logic.
Stratix II GX devices compute CRC during configuration and checks the
computed-CRC against an automatically computed CRC during normal
operation. The CRC_ERROR pin reports a soft error when configuration
SRAM data is corrupted, triggering device reconfiguration.
Custom-Built Circuitry
Dedicated circuitry is built into Stratix II GX devices to automatically
perform error detection. This circuitry constantly checks for errors in the
configuration SRAM cells while the device is in user mode. You can
monitor one external pin for the error and use it to trigger a
reconfiguration cycle. You can select the desired time between checks by
adjusting a built-in clock divider.
f
Software Interface
Beginning with version 4.1 of the Quartus II software, you can turn on the
automated error detection CRC feature in the Device & Pin Options
dialog box. This dialog box allows you to enable the feature and set the
internal frequency of the CRC between 400 kHz to 50 MHz. This controls
the rate that the CRC circuitry verifies the internal configuration SRAM
bits in the Stratix II GX FPGA.
For more information on CRC, refer to AN 357: Error Detection Using CRC
in Altera FPGA Devices.
3–12
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007