EP2SGX30CF780C5N Datasheet, PDF (67/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Stratix II GX Architecture
Figure 2–43. ALM in Shared Arithmetic Mode
shared_arith_in
carry_in
datae0
datac
datab
dataa
datad
datae1
4-Input
LUT
4-Input
LUT
4-Input
LUT
4-Input
LUT
DQ
reg0
To general or
local routing
To general or
local routing
DQ
reg1
To general or
local routing
To general or
local routing
carry_out
shared_arith_out
Note to Figure 2–43:
(1) Inputs dataf0 and dataf1 are available for register packing in shared arithmetic mode.
Adder trees are used in many different applications. For example, the
summation of the partial products in a logic-based multiplier can be
implemented in a tree structure. Another example is a correlator function
that can use a large adder tree to sum filtered data samples in a given time
frame to recover or to de-spread data which was transmitted utilizing
spread spectrum technology. An example of a three-bit add operation
utilizing the shared arithmetic mode is shown in Figure 2–44. The partial
sum (S[2..0]) and the partial carry (C[2..0]) is obtained using the
LUTs, while the result (R[2..0]) is computed using the dedicated
adders.
Altera Corporation
October 2007
2–59
Stratix II GX Device Handbook, Volume 1