EP2SGX30CF780C5N Datasheet, PDF (304/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Table 4–115. DQS Bus Clock Skew Adder Specifications
(t_DQS_CLOCK_SKEW_ADDER)
Mode
DQS Clock Skew Adder (ps) (1)
4 DQ per DQS
40
9 DQ per DQS
70
18 DQ per DQS
75
36 DQ per DQS
95
(1) This skew specification is the absolute maximum and minimum skew. For
example, skew on a 40 DQ group is 40 ps or 20 ps.
Table 4–116. DQS Phase Offset Delay Per Stage (ps) Notes (1), (2), (3)
Speed Grade
-3
-4
-5
Positive Offset
Min
Max
10
15
10
15
10
16
Negative Offset
Min
Max
8
11
8
11
8
12
(1) The delay settings are linear.
(2) The valid settings for phase offset are -32 to +31.
(3) The typical value equals the average of the minimum and maximum values.
JTAG Timing
Specifications
Figure 4–14 shows the timing requirements for the JTAG signals