EP2SGX30CF780C5N Datasheet, PDF (78/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

TriMatrix Memory
Table 2–19. TriMatrix Memory Features (Part 2 of 2)
Memory Feature
M512 RAM Block
(32 × 18 Bits)
M4K RAM Block
(128 × 36 Bits)
Simple dual-port memory
v
v
mixed width support
True dual-port memory
v
mixed width support
Power-up conditions
Outputs cleared
Outputs cleared
Register clears
Output registers
Output registers
Mixed-port read-during-write Unknown output/old data Unknown output/old data
Configurations
512 × 1
256 × 2
128 × 4
64 × 8
64 × 9
32 × 16
32 × 18
4K × 1
2K × 2
1K × 4
512 × 8
512 × 9
256 × 16
256 × 18
128 × 32
128 × 36
M-RAM Block
(4K × 144 Bits)
v
v
Outputs unknown
Output registers
Unknown output
64K × 8
64K × 9
32K × 16
32K × 18
16K × 32
16K × 36
8K × 64
8K × 72
4K × 128
4K × 144
Note to Table 2–19:
(1) Violating the setup or hold time on the memory block address registers could corrupt memory contents. This
applies to both read and write operations.
TriMatrix memory provides three different memory sizes for efficient
application support. The Quartus II software automatically partitions the
user-defined memory into the embedded memory blocks using the most
efficient size combinations. You can also manually assign the memory to
a specific block size or a mixture of block sizes.
M512 RAM Block
The M512 RAM block is a simple dual-port memory block and is useful
for implementing small FIFO buffers, DSP, and clock domain transfer
applications. Each block contains 576 RAM bits (including parity bits).
M512 RAM blocks can be configured in the following modes:
■ Simple dual-port RAM
■ Single-port RAM
■ FIFO
■ ROM
■ Shift register
When configured as RAM or ROM, you can use an initialization file to
pre-load the memory contents.
2–70
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007