EP2SGX30CF780C5N Datasheet, PDF (290/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Tables 4–98 through 4–105 show the maximum DCD in absolution
derivation for different I/O standards on Stratix II GX devices. Examples
are also provided that show how to calculate DCD as a percentage.
Table 4–98. Maximum DCD for Non-DDIO Output on Row I/O Pins
Row I/O Output Standard
3.3-V LVTTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
LVDS
Maximum DCD (ps) for Non-DDIO Output
-3 Devices -4 and -5 Devices Unit
245
275
ps
125
155
ps
105
135
ps
180
180
ps
165
195
ps
115
145
ps
95
125
ps
55
85
ps
80
100
ps
85
115
ps
55
80
ps
Here is an example for calculating the DCD as a percentage for a
non-DDIO output on a row I/O on a -3 device:
If the non-DDIO output I/O standard is SSTL-2 Class II, the maximum
DCD is 95 ps (see Table 4–99). If the clock frequency is 267 MHz, the clock
period T is:
T = 1/ f = 1 / 267 MHz = 3.745 ns = 3,745 ps
To calculate the DCD as a percentage:
(T/2 – DCD) / T = (3,745 ps/2 – 95 ps) / 3,745 ps = 47.5% (for low
boundary)
(T/2 + DCD) / T = (3,745 ps/2 + 95 ps) / 3,745 ps = 52.5% (for high
boundary)