EP2SGX30CF780C5N Datasheet, PDF (45/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Stratix II GX Architecture
The receiver PLL can also drive the regional clocks and regional routing
adjacent to the associated transceiver block. Figure 2–30 shows which
global clock resource can be used by the recovered clock. Figure 2–31
shows which regional clock resource can be used by the recovered clock.
Figure 2–30. Stratix II GX Receiver PLL Recovered Clock to Global Clock
Connection Notes (1), (2)
CLK[15..12]
11 5
7
GCLK[15..12]
Stratix II GX
Transceiver
Block
1 GCLK[3..0]
CLK[3..0]
2
GCLK[11..8]
GCLK[4..7]
Stratix II GX
Transceiver
Block
8
12 6
CLK[7..4]
Notes to Figure 2–30:
(1) CLK# pins are clock pins and their associated number. These are pins for global
and regional clocks.
(2) GCLK# pins are global clock pins.
Altera Corporation
October 2007
2–37
Stratix II GX Device Handbook, Volume 1