EP2SGX30CF780C5N Datasheet, PDF (79/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Stratix II GX Architecture
M512 RAM blocks can have different clocks on its inputs and outputs.
The wren, datain, and write address registers are all clocked together
from one of the two clocks feeding the block. The read address, rden, and
output registers can be clocked by either of the two clocks driving the
block, allowing the RAM block to operate in read and write or input and
output clock modes. Only the output register can be bypassed. The six
labclk signals or local interconnect can drive the inclock, outclock,
wren, rden, and outclr signals. Because of the advanced interconnect
between the LAB and M512 RAM blocks, ALMs can also control the wren
and rden signals and the RAM clock, clock enable, and asynchronous
clear signals. Figure 2–49 shows the M512 RAM block control signal
generation logic.
Figure 2–49. M512 RAM Block Control Signals
Dedicated
6
Row LAB
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
inclocken
outclocken
wren
inclock
outclock
rden
outclr
Altera Corporation
October 2007
2–71
Stratix II GX Device Handbook, Volume 1