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EP2SGX30CF780C5N Datasheet, PDF (231/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet | |||
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DC and Switching Characteristics
3. Simulate the output driver of choice into the actual PCB trace and
load, using the appropriate IBIS model or capacitance value to
represent the load.
4. Record the time to VMEAS.
5. Compare the results of steps 2 and 4. The increase or decrease in
delay should be added to or subtracted from the I/O Standard
Output Adder delays to yield the actual worst-case propagation
delay (clock-to-output) of the PCB trace.
The Quartus II software reports the timing with the conditions shown in
Table 4â53 using the above equation. Figure 4â8 shows the model of the
circuit that is represented by the output timing of the Quartus II software.
Figure 4â8. Output Delay Timing Reporting Setup Modeled by Quartus II
VTT
VCCIO
RT
Output Output
RS
Buffer
VMEAS
CL
Outputp
RD
Outputn
GND
GND
Notes to Figure 4â8:
(1) Output pin timing is reported at the output pin of the FPGA device. Additional
delays for loading and board trace delay need to be accounted for with IBIS model
simulations.
(2) VCCPD is 3.085 V unless otherwise specified.
(3) VCCINT is 1.12 V unless otherwise specified.
Table 4â53. Output Timing Measurement Methodology for Output Pins (Part 1 of 2) Notes (1), (2), (3)
I/O Standard
LVTTL (4)
LVCMOS (4)
2.5 V (4)
1.8 V (4)
1.5 V (4)
RS (Ω)
Loading and Termination
Measurement
Point
RD (Ω)
RT (Ω)
VCCIO (V)
3.135
3.135
2.375
1.710
1.425
VTT (V)
CL (pF)
0
0
0
0
0
VMEAS (V)
1.5675
1.5675
1.1875
0.855
0.7125
Altera Corporation
June 2009
4â61
Stratix II GX Device Handbook, Volume 1
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