EP2SGX30CF780C5N Datasheet, PDF (127/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Stratix II GX Architecture
Figure 2–82. Stratix II GX IOE in DDR Input I/O Configuration
ioe_clk[7..0]
Column, Row,
or Local
Interconnect
DQS Local
Bus (2)
Note (1)
VCCIO
To DQS Logic
Block (3)
PCI Clamp (4)
VCCIO
Programmable
Pull-Up
Resistor
sclr/spreset
clkin
ce_in
aclr/apreset
Input Pin to
Input RegisterDelay
Input Register
D
Q
ENA
CLRN/PRN
On-Chip
Termination
Bus-Hold
Circuit
Chip-Wide Reset
Input Register
D
Q
Latch
D
Q
ENA
CLRN/PRN
ENA
CLRN/PRN
Notes to Figure 2–82:
(1) All input signals to the IOE can be inverted at the IOE.
(2) This signal connection is only allowed on dedicated DQ function pins.
(3) This signal is for dedicated DQS function pins only.
(4) The optional PCI clamp is only available on column I/O pins.
Altera Corporation
October 2007
2–119
Stratix II GX Device Handbook, Volume 1