EP2SGX30CF780C5N Datasheet, PDF (131/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Stratix II GX Architecture
A compensated delay element on each DQS pin automatically aligns
input DQS synchronization signals with the data window of their
corresponding DQ data signals. The DQS signals drive a local DQS bus in
the top and bottom I/O banks. This DQS bus is an additional resource to
the I/O clocks and is used to clock DQ input registers with the DQS
signal.
The Stratix II GX device has two phase-shifting reference circuits, one on
the top and one on the bottom of the device. The circuit on the top controls
the compensated delay elements for all DQS pins on the top. The circuit
on the bottom controls the compensated delay elements for all DQS pins
on the bottom.
Each phase-shifting reference circuit is driven by a system reference clock,
which must have the same frequency as the DQS signal. Clock pins
CLK[15..12]p feed the phase circuitry on the top of the device and
clock pins CLK[7..4]p feed the phase circuitry on the bottom of the
device. In addition, PLL clock outputs can also feed the phase-shifting
reference circuits. Figure 2–86 shows the phase-shift reference circuit
control of each DQS delay shift on the top of the device. This same circuit
is duplicated on the bottom of the device.
Figure 2–86. DQS Phase-Shift Circuitry Notes (1), (2)
DQSn
Pin
DQS
Pin
DQSn
Pin
DQS
Pin
CLK[15..12]p (3)
From PLL 5 (4)
DQS
Pin
DQSn
Pin
DQS
Pin
DQSn
Pin
Δt
Δt
DQS
Δt
Δt
Phase-Shift
Δt
Δt
Circuitry
Δt
Δt
DQS Logic
Blocks
to IOE
to IOE
to IOE
to IOE
to IOE
to IOE
to IOE
to IOE
Notes to Figure 2–86:
(1) There are up to 18 pairs of DQS and DQSn pins available on the top or the bottom of the Stratix II GX device. There
are up to 10 pairs on the right side and 8 pairs on the left side of the DQS phase-shift circuitry.
(2) The “t” module represents the DQS logic block.
(3) Clock pins CLK[15..12]p feed the phase-shift circuitry on the top of the device and clock pins CLK[7..4]p feed
the phase circuitry on the bottom of the device. You can also use a PLL clock output as a reference clock to the
phaseshift circuitry.
(4) You can only use PLL 5 to feed the DQS phase-shift circuitry on the top of the device and PLL 6 to feed the DQS
phase-shift circuitry on the bottom of the device.
Altera Corporation
October 2007
2–123
Stratix II GX Device Handbook, Volume 1