EP2SGX30CF780C5N Datasheet, PDF (13/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Stratix II GX Architecture
Figure 2–3. Clock Distribution for the Transmitters Note (1)
Transmitter Channel [3..2]
TX Clock ^{Transmitter Local}
Clock Divider Block
Gen Block
Transmitter High-Speed &
Low-Speed Clocks
Reference Clocks
(refclks,
Global Clock (1),
Inter-Transceiver
Lines)
Central Block
Transmitter PLL Block
Central Clock
Divider Block
Transmitter Channel [1..0]
Note to Figure 2–3:
(1) The global clock line must be driven by an input pin.
Tra_Tns_Xmitt_Cer _lL_ooc_ca_kl
Clock Divider Block
Gen Block
Transmitter High-Speed &
Low-Speed Clocks
The transmitter PLLs in each transceiver block clock the PMA and PCS
circuitry in the transmit path. The Quartus II software automatically
powers down the transmitter PLLs that are not used in the design.
Figure 2–4 is a block diagram of the transmitter PLL.
The transmitter phase/frequency detector references the clock from one
of the following sources:
■ Reference clocks
■ Reference clock from the adjacent transceiver block
■ Inter-transceiver block clock lines
■ Global clock line driven by input pin
Two reference clocks, REFCLK0 and REFCLK1, are available per
transceiver block. The inter-transceiver block bus allows multiple
transceivers to use the same reference clocks. Each transceiver block has
one outgoing reference clock which connects to one inter-transceiver
block line. The incoming reference clock can be selected from five
inter-transceiver block lines IQ[4..0] or from the global clock line that
is driven by an input pin.
Altera Corporation
October 2007
2–5
Stratix II GX Device Handbook, Volume 1