EP2SGX30CF780C5N Datasheet, PDF (14/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Transceivers
Figure 2–4. Transmitter PLL Block Note (1)
÷m
Transmitter PLL 0
Inter-Transceiver Block
Routing (IQ[4:0])
From PLD
Dedicated Local
÷ /22
REFCLK 0
up
INCLK PFD dn CP+LF
VCO
÷L
High-Speed
Transmitter PLL0 Clock
To Inter-Transceiver
Block Line
High-Speed
Transmitter PLL Clock
Transmitter PLL 1
÷m
Inter-Transceiver Block
Routing (IQ[4:0])
From PLD
up
INCLK PFD dn ^CP+LF VCO
÷L
Dedicated Local
÷2
REFCLK 1
Note to Figure 2–4:
(1) The global clock line must be driven by an input pin.
High-Speed
Transmitter PLL1 Clock
The transmitter PLLs support data rates up to 6.375 Gbps. The input clock
frequency is limited to 622.08 MHz. An optional pll_locked port is
available to indicate whether the transmitter PLL is locked to the
reference clock. Both transmitter PLLs have a programmable loop
bandwidth parameter that can be set to low, medium, or high. The loop
bandwidth parameter can be statically set in the Quartus II software.
Table 2–2 lists the adjustable parameters in the transmitter PLL.
Table 2–2. Transmitter PLL Specifications
Parameter
Input reference frequency range
Data rate support
Multiplication factor (W)
Bandwidth
Specifications
50 MHz to 622.08 MHz
600 Mbps to 6.375 Gbps
1, 4, 5, 8, 10, 16, 20, 25
Low, medium, or high
2–6
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007