EP2SGX30CF780C5N Datasheet, PDF (5/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Introduction
f
● 8B/10B encoder and decoder perform 8-bit to 10-bit encoding
and 10-bit to 8-bit decoding
● Phase compensation FIFO buffer performs clock domain
translation between the transceiver block and the logic array
● Receiver FIFO resynchronizes the received data with the local
reference clock
● Channel aligner compliant with XAUI
Certain transceiver blocks can be bypassed. Refer to the Stratix II GX
Architecture chapter in volume 1 of the Stratix II GX Device Handbook for
more details.
Table 1–1 lists the Stratix II GX device features.
Table 1–1. Stratix II GX Device Features (Part 1 of 2)
Feature
EP2SGX30C/D
C
D
EP2SGX60C/D/E
C
D
E
ALMs
13,552
24,176
Equivalent LEs
33,880
60,440
Transceiver
channels
4
8
4
8
12
Transceiver data rate 600 Mbps to 600 Mbps to 6.375 Gbps
6.375 Gbps
Source-synchronous
31
receive channels (1)
31 31
42
Source-synchronous
29
transmit channels
29 29
42
M512 RAM blocks
202
329
(32 × 18 bits)
M4K RAM blocks
144
255
(128 × 36 bits)
M-RAM blocks
1
2
(4K × 144 bits)
Total RAM bits
1,369,728
2,544,192
Embedded
64
144
multipliers (18 × 18)
DSP blocks
16
36
PLLs
4
4
4
8
Maximum user I/O
pins
361
364 364 534
EP2SGX90E/F
E
F
36,384
90,960
12
16
600 Mbps to
6.375 Gbps
47
59
45
59
488
408
4
4,520,448
192
48
8
558
650
EP2SGX130/G
G
53,016
132,540
20
600 Mbps to
6.375 Gbps
73
71
699
609
6
6,747,840
252
63
8
734
Altera Corporation
October 2007
1–3
Stratix II GX Device Handbook, Volume 1