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EP2SGX30CF780C5N Datasheet, PDF (11/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet | |||
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Altera Corporation
October 2007
Stratix II GX Architecture
Figure 2â2. Elements of the Transceiver Block
Stratix II GX
Logic Array
Transceiver Block
Channel 1
Channel 0
Supporting Blocks
(PLLs, State Machines,
Programming)
Channel 2
Channel 3
RX1
TX1
RX0
TX0
REFCLK_1
REFCLK_0
RX2
TX2
RX3
TX3
Each Stratix II GX transceiver channel consists of a transmitter and
receiver. The transceivers are grouped in four and share PLL resources.
Each transmitter has access to one of two PLLs. The transmitter contains
the following:
â Transmitter phase compensation first-in first-out (FIFO) buffer
â Byte serializer (optional)
â 8B/10B encoder (optional)
â Serializer (parallel-to-serial converter)
â Transmitter differential output buffer
The receiver contains the following:
â Receiver differential input buffer
â Receiver lock detector and run length checker
â Clock recovery unit (CRU)
â Deserializer
â Pattern detector
â Word aligner
â Lane deskew
â Rate matcher (optional)
â 8B/10B decoder (optional)
â Byte deserializer (optional)
â Byte ordering
â Receiver phase compensation FIFO buffer
Designers can preset Stratix II GX transceiver functions using the
Quartus® II software. In addition, pre-emphasis, equalization, and
differential output voltage (VOD) are dynamically programmable. Each
Stratix II GX transceiver channel supports various loopback modes and is
2â3
Stratix II GX Device Handbook, Volume 1
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