EP2SGX30CF780C5N Datasheet, PDF (38/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Transceivers
When the FIFO pointers initialize, the receiver domain clock must remain
phase locked to receiver FPGA clock.
After resetting the receiver FIFO buffer, writing to the receiver FIFO
buffer begins and continues on each parallel clock. The phase
compensation FIFO buffer is eight words deep for PIPE mode and four
words deep for all other modes.
Loopback Modes
The Stratix II GX transceiver has built-in loopback modes for debugging
and testing. The loopback modes are configured in the Stratix II GX
ALT2GXB megafunction in the Quartus II software. The available
loopback modes are:
■ Serial loopback
■ Parallel loopback
■ Reverse serial loopback
■ Reverse serial loopback (pre-CDR)
■ PCI Express PIPE reverse parallel loopback (available only in PIPE
mode)
Serial Loopback
The serial loopback mode exercises all the transceiver logic, except for the
input buffer. Serial loopback is available for all non-PIPE modes. The
loopback function is dynamically enabled through the
rx_seriallpbken port on a channel-by-channel basis.
In serial loopback mode, the data on the transmit side is sent by the PLD.
A separate mode is available in the ALT2GXB megafunction under Basic
protocol mode, in which PRBS data is generated and verified internally in
the transceiver. The PRBS patterns available in this mode are shown in
Table 2–10.
Table 2–10 shows the BIST data output and verifier alignment pattern.
Table 2–10. BIST Data Output and Verifier Alignment Pattern
Pattern
PRBS-7
PRBS-10
Polynomial
×7 + ×6 + 1
×10 + ×7 + 1
8-Bit
Parallel Data Width
10-Bit 16-Bit
v
20-Bit
v
2–30
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007