EP2SGX30CF780C5N Datasheet, PDF (292/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Table 4–100. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -3 Devices
Note (1)
Input I/O Standard (No PLL in Clock Path)
Maximum DCD (ps) for
Row DDIO Output I/O
Standard
TTL/CMOS
3.3 and
2.5 V
1.8 and
1.5 V
SSTL-2
2.5 V
SSTL/HSTL
1.8 and
1.5 V
LVDS
Unit
3.3 V
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
LVDS
260
380
145
145
210
330
100
100
195
315
85
85
150
265
85
85
255
370
140
140
175
295
65
65
170
290
60
60
155
275
55
50
150
270
60
60
150
270
55
55
180
180
180
180
110
ps
65
ps
75
ps
120
ps
105
ps
70
ps
75
ps
90
ps
95
ps
90
ps
180
ps
(1) The information in Table 4–100 assumes the input clock has zero DCD.
Here is an example for calculating the DCD in percentage for a DDIO
output on a row I/O on a -3 device:
If the input I/O standard is 2.5-V SSTL-2 and the DDIO output I/O
standard is SSTL-2 Class= II, the maximum DCD is 60 ps (see
Table 4–100). If the clock frequency is 267 MHz, the clock period T is:
T = 1/ f = 1 / 267 MHz = 3.745 ns = 3,745 ps
Calculate the DCD as a percentage:
(T/2 – DCD) / T = (3,745 ps/2 – 60 ps) / 3745 ps = 48.4% (for low
boundary)
(T/2 + DCD) / T = (3,745 ps/2 + 60 ps) / 3745 ps = 51.6% (for high
boundary)