EP2SGX30CF780C5N Datasheet, PDF (4/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Features
● Support for multiple intellectual property megafunctions from
Altera^® MegaCore^® functions and Altera Megafunction Partners
Program (AMPP^SM) megafunctions
● Support for design security using configuration bitstream
encryption
● Support for remote configuration updates
■ Transceiver block features:
● High-speed serial transceiver channels with clock data recovery
(CDR) provide 600-megabits per second (Mbps) to 6.375-Gbps
full-duplex transceiver operation per channel
● Devices available with 4, 8, 12, 16, or 20 high-speed serial
transceiver channels providing up to 255 Gbps of serial
bandwidth (full duplex)
● Dynamically programmable voltage output differential (V_OD)
and pre-emphasis settings for improved signal integrity
● Support for CDR-based serial protocols, including PCI Express,
Gigabit Ethernet, SDI, Altera’s SerialLite II, XAUI, CEI-6G,
CPRI, Serial RapidIO, SONET/SDH
● Dynamic reconfiguration of transceiver channels to switch
between multiple protocols and data rates
● Individual transmitter and receiver channel power-down
capability for reduced power consumption during
non-operation
● Adaptive equalization (AEQ) capability at the receiver to
compensate for changing link characteristics
● Selectable on-chip termination resistors (100, 120, or 150 Ω) for
improved signal integrity on a variety of transmission media
● Programmable transceiver-to-FPGA interface with support for
8-, 10-, 16-, 20-, 32-, and 40-bit wide data transfer
● 1.2- and 1.5-V pseudo current mode logic (PCML) for 600 Mbps
to 6.375 Gbps (AC coupling)
● Receiver indicator for loss of signal (available only in PIPE
mode)
● Built-in self test (BIST)
● Hot socketing for hot plug-in or hot swap and power
sequencing support without the use of external devices
● Rate matcher, byte-reordering, bit-reordering, pattern detector,
and word aligner support programmable patterns
● Dedicated circuitry that is compliant with PIPE, XAUI, and
GIGE
● Built-in byte ordering so that a frame or packet always starts in
a known byte lane
● Transmitters with two PLL inputs for each transceiver block
with independent clock dividers to provide varying clock rates
on each of its transmitters
1–2
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007