EP2SGX30CF780C5N Datasheet, PDF (150/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Referenced Documents
Figure 2–91. Fast PLL and Channel Layout in the EP2SGX60E to EP2SGX130 Devices Note (1)
Fast
PLL 7
2
4
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
4
2
Fast
PLL 1
Fast
PLL 2
2
LVDS
4
Clock
DPA
Clock
Quadrant
Quadrant
2
Fast
PLL 8
Note to Figure 2–91:
(1) See Tables 2–39 through Tables 2–41 for the number of channels each device supports.
Referenced
Documents
This chapter references the following documents:
■ DC & Switching Characteristics chapter in volume 1 of the Stratix II GX
Handbook
■ DSP Blocks in Stratix II GX Devices chapter in Volume 2 of the
Stratix II GX Device Handbook
■ External Memory Interfaces in Stratix II & Stratix II GX Devices chapter
in volume 2 of the Stratix II GX Device Handbook
■ High-Speed Differential I/O Interfaces with DPA in Stratix II & Stratix II
GX Devices chapter in volume 2 of the Stratix II GX Handbook
■ PLLs in Stratix II & Stratix II GX Devices chapter in volume 2 of the
Stratix II GX Device Handbook
■ Selectable I/O Standards in Stratix II & Stratix II GX Devices chapter in
volume 2 of the Stratix II GX Handbook
■ Stratix II GX Device Handbook, volume 2
■ Stratix II GX Transceiver Architecture Overview chapter in volume 2 of
the Stratix II GX Handbook
2–142
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007