EP2SGX30CF780C5N Datasheet, PDF (154/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Document Revision History
Table 2–42. Document Revision History (Part 4 of 6)
Date and
Document
Version
Changes Made
Updated:
● “Transmitter PLLs”
● “Transmitter Phase Compensation FIFO
Buffer”
● “8B/10B Encoder”
● “Byte Serializer”
● “Programmable Output Driver”
● “Receiver PLL & CRU”
● “Programmable Pre-Emphasis”
● “Receiver Input Buffer”
● “Control and Status Signals”
● “Programmable Run Length Violation”
● “Channel Aligner”
● “Basic Mode”
● “Byte Ordering Block”
● “Receiver Phase Compensation FIFO
Buffer”
● “Loopback Modes”
● “Serial Loopback”
● “Parallel Loopback”
● “Regional Clock Network”
● “MultiVolt I/O Interface”
● “High-Speed Differential I/O with DPA
Support”
Updated bulleted lists at the beginning of the
“Transceivers” section.
Added reference to the “Transmit Buffer”
section.
Deleted the Programmable V_OD table from the
“Programmable Output Driver” section.
Changed “PLD Interface” heading to “Parallel
Data Width” heading in Table 2–14.
Deleted “Global & Regional Clock
Connections from Right Side Clock Pins &
Fast PLL Outputs” table.
Updated notes to Tables 2–29 and 2–37.
Updated notes to Figures 2–72, 2–73 and
2–74.
Updated bulleted list in the “Advanced I/O
Standard Support” section.
Summary of Changes
2–146
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007