EP2SGX30CF780C5N Datasheet, PDF (253/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Table 4–81. Stratix II GX IOE Programmable Delay on Row Pins Note (1)
Parameter
Minimum
-3 Speed
-3 Speed
-4 Speed
-5 Speed
Paths Available ^Timing
Affected Settings _{Min Max}
Grade
Min Max
Grade
Min Max
Grade
Min Max
Grade
Unit
Min Max
Offset Offset Offset Offset Offset Offset Offset Offset Offset Offset
Input delay Pad to I/O
8
from pin to dataout to
internal logic array
cells
0 1782 0 2876 0 3020 0 3212 0 3853 ps
Input delay Pad to I/O 64
from pin to input
input
register
register
0 2054 0 3270 0 3434 0 3652 0 4381 ps
Delay from I/O output
2
output
register to
register to pad
output pin
0 332 0 500 0 525 0 559 0 670 ps
Output
enable pin
delay
t_XZ, t_ZX
2
0 320 0 483 0 507 0 539 0 647 ps
(1) The incremental values for the settings are generally linear. For the exact delay associated with each setting, use the latest
version of the Quartus II software.
Default Capacitive Loading of Different I/O Standards
See Table 4–82 for default capacitive loading of different I/O standards.
Table 4–82. Default Loading of Different I/O Standards for Stratix II GX
Devices (Part 1 of 2)
I/O Standard
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
PCI
PCI-X
SSTL-2 Class I
SSTL-2 Class II
Capacitive Load
Unit
0
pF
0
pF
0
pF
0
pF
0
pF
10
pF
10
pF
0
pF
0
pF