EP2SGX30CF780C5N Datasheet, PDF (110/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

PLLs and Clock Networks
Figure 2–72. Global and Regional Clock Connections from Corner Clock Pins and Fast PLL
Outputs Notes (1), (2)
RCLK1
RCLK3
RCLK0
RCLK2
C0
Fast C1
PLL 7
C2
C3
C0
Fast C1
PLL 8
C2
C3
RCLK4
RCLK6
GCLK0
GCLK2
RCLK5
RCLK7
GCLK1
GCLK3
Notes to Figure 2–72:
(1) The global or regional clocks in a fast PLL’s quadrant can drive the fast PLL input. A dedicated clock input pin or
other PLL must drive the global or regional source. The source cannot be driven by internally generated logic before
driving the fast PLL.
(2) EP2SGX30C/D and EP2SGX60C/D devices only have two fast PLLs (1 and 2); they do not contain corner fast
PLLs.
Table 2–27. Global and Regional Clock Connections from Left Side Clock Pins and Fast PLL Outputs
(Part 1 of 3)
Left Side Global and Regional
Clock Network Connectivity
Clock pins
CLK0p
CLK1p
CLK2p
CLK3p
vv
v
vv
v
vv
v
v
v
v
vv
v
v
2–102
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007