EP2SGX30CF780C5N Datasheet, PDF (35/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Stratix II GX Architecture
Figure 2–21. 8B/10B Decoder
dataout[15..8]
To Byte
Deserializer
Status Signals[1] (1)
dataout[7..0]
Status Signals[0] (1)
8B/10B
Decoder
MSByte
8B/10B
Decoder
LSByte
datain[19..10]
From Rate
Matcher
datain[9..0]
The 8B/10B decoder in single-width mode translates the 10-bit encoded
data into the 8-bit equivalent data or control code. The 10-bit code
received must be from the supported Dx.y or Kx.y list with the proper
disparity or error flags asserted. All 8B/10B control signals, such as
disparity error or control detect, are pipelined with the data and
edge-aligned with the data. Figure 2–22 shows how the 10-bit symbol is
decoded in the 8-bit data + 1-bit control indicator.
Figure 2–22. 8B/10B Decoder Conversion
j hg f i e dc b a
9 87 65 4 3 21 0
MSB received last
8B/10B conversion
LSB received first
Parallel data 7 6 5 4 3
HG FE D
21
CB
0 ⁺ ctrl
A
The 8B/10B decoder in double-width mode translates the 20-bit
(2 × 10-bits) encoded code into the 16-bit (2 × 8-bits) equivalent data or
control code. The 20-bit upper and lower symbols received must be from
the supported Dx.y or Kx.y list with the proper disparity or error flags
Altera Corporation
October 2007
2–27
Stratix II GX Device Handbook, Volume 1