EP2SGX30CF780C5N Datasheet, PDF (232/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Timing Model
Table 4–53. Output Timing Measurement Methodology for Output Pins (Part 2 of 2) Notes (1), (2), (3)
I/O Standard
R_S (Ω)
PCI (5)
PCI-X (5)
SSTL-2 Class I
25
SSTL-2 Class II
25
SSTL-18 Class I
25
SSTL-18 Class II
25
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL with OCT
Differential SSTL-2 Class I
25
Differential SSTL-2 Class II
25
Differential SSTL-18 Class I
50
Differential SSTL-18 Class II
25
1.5-V differential HSTL Class I
1.5-V differential HSTL Class II
1.8-V differential HSTL Class I
1.8-V differential HSTL Class II
LVDS
LVPECL
Loading and Termination
Measurement
Point
R_D (Ω)
100
100
R_T (Ω)
50
25
50
25
50
25
50
25
50
25
50
25
50
25
50
25
V_CCIO (V)
2.970
2.970
2.325
2.325
1.660
1.660
1.660
1.660
1.375
1.375
1.140
2.325
2.325
1.660
1.660
1.375
1.375
1.660
1.660
2.325
3.135
V_TT (V)
1.123
1.123
0.790
0.790
0.790
0.790
0.648
0.648
1.123
1.123
0.790
0.790
0.648
0.648
0.790
0.790
C_L (pF)
10
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
V_MEAS (V)
1.485
1.485
1.1625
1.1625
0.83
0.83
0.83
0.83
0.6875
0.6875
0.570
1.1625
1.1625
0.83
0.83
0.6875
0.6875
0.83
0.83
1.1625
1.5675
Notes to Table 4–53:
(1) Input measurement point at internal node is 0.5 V_CCINT.
(2) Output measuring point for V_MEAS at buffer output is 0.5 V_CCIO.
(3) Input stimulus edge rate is 0 to V_CC in 0.2 ns (internal signal) from the driver preceding the I/O buffer.
(4) Less than 50-mV ripple on V_CCIO and V_CCPD, V_CCINT = 1.15 V with less than 30-mV ripple.
(5) V_CCPD = 2.97 V, less than 50-mV ripple on V_CCIO and V_CCPD, V_CCINT = 1.15 V.
4–62
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009