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EP2SGX30CF780C5N Datasheet, PDF (147/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet | |||
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Figure 2â88. Stratix II GX Transmitter Channel
Data from R4, R24, C4, or
direct link interconnect
10
10
Stratix II GX Architecture
+
Up to 1 Gbps
â
refclk
Local
Interconnect
diffioclk
Fast
PLL
load_en
Dedicated
Transmitter
Interface
Regional or
global clock
Each Stratix II GX receiver channel features a DPA block for phase
detection and selection, a SERDES, a synchronizer, and a data realigner
circuit. You can bypass the dynamic phase aligner without affecting the
basic source-synchronous operation of the channel. In addition, you can
dynamically switch between using the DPA block or bypassing the block
via a control signal from the logic array.
Altera Corporation
October 2007
2â139
Stratix II GX Device Handbook, Volume 1
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