EP2SGX30CF780C5N Datasheet, PDF (106/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

PLLs and Clock Networks
The Quartus II software enables the PLLs and their features without
requiring any external devices. Table 2–25 shows the PLLs available for
each Stratix II GX device and their type.
Table 2–25. Stratix II GX Device PLL Availability Notes (1), (2)
Device
Fast PLLs
Enhanced PLLs
1 2 3 (3) 4 (3) 7
8 9 (3) 10 (3) 5 6 11
12
EP2SGX30 v v
vv
EP2SGX60 v v
vv
vv v
v
EP2SGX90 v v
vv
vv v
v
EP2SGX130 v v
vv
vv v
v
Notes to Table 2–25:
(1) EP2SGX30C/D and EP2SGX60C/D devices only have two fast PLLs (1 and 2), but the connectivity from these two
PLLs to the global and regional clock networks remains the same as shown. The EP2S60C/D devices only have
two enhanced PLLs (5 and 6).
(2) The global or regional clocks in a fast PLL’s quadrant can drive the fast PLL input. A dedicated clock input pin or
other PLL must drive the global or regional source. The source cannot be driven by internally generated logic
before driving the fast PLL.
(3) PLLs 3, 4, 9, and 10 are not available in Stratix II GX devices. However, these PLLs are listed in Table 2–25 because
the Stratix II GX PLL numbering scheme is consistent with Stratix and Stratix II devices.
2–98
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007