EP2SGX30CF780C5N Datasheet, PDF (129/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Stratix II GX Architecture
Figure 2–84. Stratix II GX IOE in DDR Output I/O Configuration
ioe_clk[7..0]
Column, Row,
or Local
Interconnect
Notes (1), (2)
oe
clkout
ce_out
OE Register
D
Q
ENA
CLRN/PRN
OE Register
tCO Delay
aclr/apreset
Chip-Wide Reset
sclr/spreset
OE Register
D
Q
ENA
CLRN/PRN
Used for
DDR, DDR2
SDRAM
VCCIO
PCI Clamp (3)
VCCIO
Programmable
Pull-Up
Resistor
Output Register
D
Q
Output
Pin Delay
ENA
CLRN/PRN
Output Register
D
Q
clk
Drive Strength
Control
Open-Drain Output
ENA
CLRN/PRN
On-Chip
Termination
Bus-Hold
Circuit
Notes to Figure 2–84:
(1) All input signals to the IOE can be inverted at the IOE.
(2) The tri-state buffer is active low. The DDIO megafunction represents the tri-state buffer as active-high with an
inverter at the OE register data port.
(3) The optional PCI clamp is only available on column I/O pins.
Altera Corporation
October 2007
2–121
Stratix II GX Device Handbook, Volume 1