EP2SGX30CF780C5N Datasheet, PDF (206/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Operating Conditions
Table 4–19. Stratix II GX Transceiver Block AC Specification Notes (1), (2), (3) (Part 19 of 19)
Symbol/
Description
Conditions
-3 Speed
Commercial Speed
Grade
-4 Speed
Commercial and
Industrial Speed
Grade
-5 Speed
Commercial Speed
Grade
Unit
Min Typ Max Min Typ Max Min Typ Max
Notes to Table 4–19:
(1) Dedicated REFCLK pins were used to drive the input reference clocks.
(2) Jitter numbers specified are valid for the stated conditions only.
(3) Refer to the protocol characterization documents for detailed information.
(4) HiGig configuration is available in a -3 speed grade only. For more information, refer to the Stratix II GX Transceiver
Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook.
(5) Stratix II GX transceivers meet CEI jitter generation specification of 0.3 UI for a V_OD range of 400 mV to 1000 mV.
(6) The Sinusoidal Jitter Tolerance Mask is defined only for low voltage (LV) variant of CPRI.
(7) The jitter numbers for SONET/SDH are compliant to the GR-253-CORE Issue 3 Specification.
(8) The jitter numbers for Fibre Channel are compliant to the FC-PI-4 Specification revision 6.10.
(9) The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification.
(10) The jitter numbers for PCI Express are compliant to the PCIe Base Specification 2.0.
(11) The jitter numbers for Serial RapidIO are compliant to the RapidIO Specification 1.3.
(12) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
(13) The jitter numbers for HiGig are compliant to the IEEE802.3ae-2002 Specification.
(14) The jitter numbers for (OIF) CEI are compliant to the OIF-CEI-02.0 Specification.
(15) The jitter numbers for CPRI are compliant to the CPRI Specification V2.1.
(16) The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M Specifications.
(17) The Fibre Channel transmitter jitter generation numbers are compliant to the specification at β_T interoperability point.
(18) The Fibre Channel receiver jitter tolerance numbers are compliant to the specification at β_R interoperability point.
Table 4–20 provides information on recommended input clock jitter for
each mode.
Table 4–20. Recommended Input Clock Jitter (Part 1 of 2)
Mode
PCI-E
(OIF) CEI
PHY
GIGE
XAUI
Reference
Clock (MHz)
100
156.25
622.08
62.5
125
156.25
Vectron
LVPECL XO
Type/Model
VCC6-Q/R
VCC6-Q/R
VCC6-Q
VCC6-Q/R
VCC6-Q/R
VCC6-Q/R
Frequency
Range (MHz)
RMS Jitter
(12 kHz to 20
MHz) (ps)
10 to 270
0.3
10 to 270
0.3
270 to 800
2
10 to 270
0.3
10 to 270
0.3
10 to 270
0.3
Period Jitter
(Peak to
Peak) (ps)
23
23
30
23
23
23
Phase Noise
at 1 MHz
(dB c/Hz)
-149.9957
-146.2169
Not available
-149.9957
-146.9957
-146.2169
4–36
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009