EP2SGX30CF780C5N Datasheet, PDF (44/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Transceivers
Figure 2–29. EP2SGX130 Device Inter-Transceiver and Global Clock Connections
To PLD
Global Clocks
From Global
Clock Line (3)
16 Interface Clocks
Global clk line
IQ[4..0]
To IQ0
Transceiver Block 0
REFCLK0
÷2
Transmitter
PLL 0
IQ[4..0]
Global clk line
IQ[4..0]
IQ[4..0]
Global clk line
IQ[4..0]
To IQ1
REFCLK1
÷2
Transmitter
PLL 1
From Global Clock Line (3)
Transceiver Block 1
REFCLK0
÷2
Transceiver Clock Generator Block
Transmitter
PLL 0
4
Receiver
PLLs
IQ[4..0]
Global clk line
IQ[4..0]
Global clk line
IQ[4..0]
To IQ4
REFCLK1
÷2
Transmitter
PLL 1
From Global Clock Line (3)
Transceiver Block 2
REFCLK0
÷2
Transceiver Clock Generator Block
Transmitter
PLL 0
4
Receiver
PLLs
IQ[4..0]
Global clk line
Global clk line
IQ[4..0]
To IQ2
REFCLK1
÷2
Transmitter
PLL 1
IQ[4..0]
From Global Clock Line (3)
Transceiver Block 3
REFCLK0
÷2
Transceiver Clock Generator Block
Transmitter
PLL 0
4
Receiver
PLLs
IQ[4..0]
Global clk line
IQ[4..0]
Global clk line
IQ[4..0]
To IQ3
REFCLK1
÷2
Transmitter
PLL 1
From Global Clock Line (3)
Transceiver Block 4
REFCLK0
÷2
Transceiver Clock Generator Block
Transmitter
PLL 0
4
Receiver
PLLs
IQ[4..0]
Global clk line
IQ[4..0]
REFCLK1
Transmitter
÷2
PLL 1
From Global Clock Line (3)
Transceiver Clock Generator Block
4
Receiver
PLLs
Notes to Figure 2–29:
(1) There are two transmitter PLLs in each transceiver block.
(2) There are four receiver PLLs in each transceiver block.
(3) The Global Clock line must be driven by an input pin.
2–36
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007