EP2SGX30CF780C5N Datasheet, PDF (208/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Operating Conditions
Table 4–21. PCS Latency (Part 2 of 2) Note (1)
Transmitter PCS Latency
Functional Mode
Configuration
TX PIPE
TX
Phase
Comp
FIFO
Byte TX State
Serializer Machine
Serial RapidIO
1.25 Gbps,
-
2-3
1
-
2.5 Gbps,
3.125 Gbps
SDI
HD
-
2-3
1
-
10-bit channel
width
HD, 3G
-
2-3
1
-
20-bit channel
width
8-bit/10-bit
-
2-3
1
-
BASIC Single
channel width
Width
16-bit/20-bit
-
2-3
1
-
channel width
16-bit/20-bit
-
2-3
1
-
channel width
BASIC Double
Width
32-bit/40-bit
-
channel width
2-3
1
-
Parallel
-
2-3
1
-
Loopback/
BIST
8B/10B
Encoder
0.5
1
0.5
1
0.5
1
0.5
1
Sum (2)
4-5
4-5
4-5
4-5
4-5
4-5
4-5
4-5
Notes to Table 4–21:
(1) The latency numbers are with respect to the PLD-transceiver interface clock cycles.
(2) The total latency number is rounded off in the Sum column.
(3) For CPRI 614 Mbps and 1.228 Gbps data rates, the Quartus II software customizes the PLD-transceiver
interface clocking to achieve zero clock cycle uncertainty in the transmitter phase compensation FIFO
latency. For more details, refer to the CPRI Mode section in the Stratix II GX Transceiver Architecture Overview
chapter in volume 2 of the Stratix II GX Device Handbook.
4–38
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009