EP2SGX30CF780C5N Datasheet, PDF (269/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

To calculate the output toggle rate for a non 0 pF load, use this formula:
The toggle rate for a non 0 pF load
= 1,000 / (1,000/ toggle rate at 0 pF load + derating factor × load
value in pF /1,000)
For example, the output toggle rate at 0 pF load for SSTL-18 Class II
20 mA I/O standard is 550 MHz on a -3 device clock output pin. The
derating factor is 94 ps/pF. For a 10 pF load the toggle rate is calculated
as:
1,000 / (1,000/550 + 94 × 10 /1,000) = 363 (MHz)
Table 4–88 shows the maximum input clock toggle rates for Stratix II GX
device column pins.
Table 4–88. Stratix II GX Maximum Input Clock Rate for Column I/O Pins (Part 1 of 2)
I/O Standard
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class I I
1.5-V HSTL Class I
1.5-V HSTL Class I I
1.8-V HSTL Class I
1.8-V HSTL Class II
PCI
PCI-X
Differential SSTL-2
Class I
Differential SSTL-2
Class II
Differential SSTL-18
Class I
-3 Speed Grade
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
-4 Speed Grade
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
-5 Speed Grade
450
450
450
450
450
500
500
500
500
500
500
500
500
450
450
500
500
500
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz