EP2SGX30CF780C5N Datasheet, PDF (161/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Configuration & Testing
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The nIO_PULLUP pin is a dedicated input that chooses whether the
internal pull-up resistors on the user I/O pins and dual-purpose
configuration I/O pins (nCSO, ASDO, DATA[7..0], nWS, nRS, RDYnBSY,
nCS, CS, RUnLU, PGM[2..0], CLKUSR, INIT_DONE, DEV_OE, DEV_CLR)
are on or off before and during configuration. A logic high (1.5, 1.8, 2.5,
3.3 V) turns off the weak internal pull-up resistors, while a logic low turns
them on.
Stratix II GX devices also offer a new power supply, V_CCPD, which must
be connected to 3.3 V in order to power the 3.3-V/2.5-V buffer available
on the configuration input pins and JTAG pins. V_CCPD applies to all the
JTAG input pins (TCK, TMS, TDI, and TRST) and the following
configuration pins: nCONFIG, DCLK (when used as an input),
nIO_PULLUP, DATA[7..0], RUnLU, nCE, nWS, nRS, CS, nCS, and
CLKUSR. The VCCSEL pin allows the V_CCIO setting (of the banks where the
configuration inputs reside) to be independent of the voltage required by
the configuration inputs. Therefore, when selecting the V_CCIO voltage,
you do not have to take the V_IL and V_IH levels driven to the configuration
inputs into consideration. The configuration input pins, nCONFIG, DCLK
(when used as an input), nIO_PULLUP, RUnLU, nCE, nWS, nRS, CS, nCS,
and CLKUSR, have a dual buffer design: a 3.3-V/2.5-V input buffer and a
1.8-V/1.5-V input buffer. The V_CCSEL input pin selects which input buffer
is used. The 3.3-V/2.5-V input buffer is powered by V_CCPD, while the 1.8-
V/1.5-V input buffer is powered by V_CCIO.
V_CCSEL is sampled during power-up. Therefore, the V_CCSEL setting cannot
change on-the-fly or during a reconfiguration. The V_CCSEL input buffer is
powered by V_CCINT and must be hardwired to V_CCPD or ground. A logic
high V_CCSEL connection selects the 1.8-V/1.5-V input buffer; a logic low
selects the 3.3-V/2.5-V input buffer. V_CCSEL should be set to comply with
the logic levels driven out of the configuration device or the MAX II
microprocessor.
If the design must support configuration input voltages of 3.3 V/2.5 V, set
V_CCSEL to a logic low. You can set the V_CCIO voltage of the I/O bank that
contains the configuration inputs to any supported voltage. If the design
must support configuration input voltages of 1.8 V/1.5 V, set V_CCSEL to a
logic high and the V_CCIO of the bank that contains the configuration
inputs to 1.8 V/1.5 V.
For more information on multi-volt support, including information on
using TDO and nCEO in multi-volt systems, refer to the Stratix II GX
Architecture chapter in volume 1 of the Stratix II GX Device Handbook.
Altera Corporation
October 2007
3–5
Stratix II GX Device Handbook, Volume 1