EP2SGX30CF780C5N Datasheet, PDF (229/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

DC and Switching Characteristics
Power
Consumption
f
Altera offers two ways to calculate power for a design: the Excel-based
PowerPlay early power estimator power calculator and the Quartus^® II
PowerPlay power analyzer feature.
The interactive Excel-based PowerPlay early power estimator is typically
used prior to designing the FPGA in order to get an estimate of device
power. The Quartus II PowerPlay power analyzer provides better quality
estimates based on the specifics of the design after place-and-route is
complete. The power analyzer can apply a combination of user-entered,
simulation-derived and estimated signal activities which, combined with
detailed circuit models, can yield very accurate power estimates.
In both cases, these calculations should only be used as an estimation of
power, not as a specification.
For more information on PowerPlay tools, refer to the PowerPlay Early
Power Estimators (EPE) and Power Analyzer, the Quartus II PowerPlay
Analysis and Optimization Technology, and the PowerPlay Power Analyzer
chapter in volume 3 of the Quartus II Handbook. The PowerPlay early
power estimators are available on the Altera web site at
www.altera. com.
1 See Table 4–23 on page 42 for typical I_CC standby specifications.
Timing Model
The DirectDrive technology and MultiTrack interconnect ensure
predictable performance, accurate simulation, and accurate timing
analysis across all Stratix II GX device densities and speed grades. This
section describes and specifies the performance, internal, external, and
PLL timing specifications.
All specifications are representative of worst-case supply voltage and
junction temperature conditions.
Preliminary and Final Timing
Timing models can have either preliminary or final status. The Quartus II
software issues an informational message during the design compilation
if the timing models are preliminary. Table 4–52 shows the status of the
Stratix II GX device timing models.
Preliminary status means the timing model is subject to change. Initially,
timing numbers are created using simulation results, process data, and
other known parameters. These tests are used to make the preliminary
numbers as close to the actual timing parameters as possible.
Altera Corporation
June 2009
4–59
Stratix II GX Device Handbook, Volume 1