EP2SGX30CF780C5N Datasheet, PDF (176/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Operating Conditions
Table 4–6. Stratix II GX Transceiver Block AC Specification (Part 3 of 6)
Symbol /
Description
Conditions
reconfig_c
lk clock
frequency
Transceiver
block minimum
power-down
pulse width
Receiver
Data rate
Absolute V_{M A X}
for a receiver
pin (1)
Absolute V_{M I N}
for a receiver
pin
Maximum
peak-to-peak
differential
input voltage
V_{I D} (diff p-p)
V_{C M} = 0.85 V
Minimum
peak-to-peak
differential
input voltage
V_{I D} (diff p-p)
V_{C M} = 0.85 V
DC Gain =
≥ 3 dB
V_{I C M}
V_{I C M} = 0.85
V setting
V_{I C M} = 1.2 V
setting (11)
On-chip
termination
resistors
100 Ω setting
120 Ω setting
150 Ω setting
Bandwidth at
6.375 Gbps
BW = Low
BW = Med
BW = High
-3 Speed Commercial
Speed Grade
Min Typ Max
2.5
-
50
100
-
-
600
- 6375
-
-
2.0
-0.4
-
-
-
-
3.3
160
-
-
850±10%
1200±10%
100±15%
120±15%
150±15%
-
20
-
-
35
-
-
45
-
-4 Speed Commercial
and Industrial Speed
Grade
-5 Speed Commercial
Speed Grade
Unit
Min Typ Max Min Typ Max
2.5
-
50
2.5
-
50 MHz
100
-
-
100
-
- ns
600
-
5000 600
- 4250 Mbps
-
-
2.0
-
-
2.0
V
-0.4
-
-
-0.4
-
-
V
-
-
3.3
-
-
3.3
V
160
-
-
160
-
-
mV
850±10%
1200±10%
100±15%
120±15%
150±15%
-
-
-
-
-
-
-
-
-
850±10%
1200±10%
100±15%
120±15%
150±15%
-
-
-
-
-
-
-
-
-
mV
mV
Ω
Ω
Ω
MHz
MHz
MHz
4–6
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009