EP2SGX30CF780C5N Datasheet, PDF (138/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

I/O Structure
On-Chip Termination
Stratix II GX devices provide differential (for the LVDS technology I/O
standard) and series on-chip termination to reduce reflections and
maintain signal integrity. On-chip termination simplifies board design by
minimizing the number of external termination resistors required.
Termination can be placed inside the package, eliminating small stubs
that can still lead to reflections.
Stratix II GX devices provide four types of termination:
■ Differential termination (R_D)
■ Series termination (R_S) without calibration
■ Series termination (R_S) with calibration
■ Parallel termination (R_T) with calibration
Table 2–34 shows the Stratix II GX on-chip termination support per I/O
bank.
Table 2–34. On-Chip Termination Support by I/O Banks (Part 1 of 2)
On-Chip Termination Support I/O Standard Support
Series termination without
calibration
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL
2.5-V LVCMOS
1.8-V LVTTL
1.8-V LVCMOS
1.5-V LVTTL
1.5-V LVCMOS
SSTL-2 class I and II
SSTL-18 class I
SSTL-18 class II
1.8-V HSTL class I
1.8-V HSTL class II
1.5-V HSTL class I
1.2-V HSTL
Top and Bottom Banks
(3, 4, 7, 8)
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Left Bank (1, 2)
v
v
v
v
v
v
v
v
v
v
—
v
—
v
—
2–130
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007