EP2SGX30CF780C5N Datasheet, PDF (83/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Stratix II GX Architecture
Figure 2–52. M4K RAM Block LAB Row Interface
C4 Interconnect
Direct link
16
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
36
dataout
M4K RAM
Block
datain
control
signals
clocks
byte
enable
address
R4 Interconnect
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
6
M4K RAM Block Local
Interconnect Region
LAB Row Clocks
M-RAM Block
The largest TriMatrix memory block, the M-RAM block, is useful for
applications where a large volume of data must be stored on-chip. Each
block contains 589,824 RAM bits (including parity bits). The M-RAM
block can be configured in the following modes:
■ True dual-port RAM
■ Simple dual-port RAM
■ Single-port RAM
■ FIFO
You cannot use an initialization file to initialize the contents of a M-RAM
block. All M-RAM block contents power up to an undefined value. Only
synchronous operation is supported in the M-RAM block, so all inputs
are registered. Output registers can be bypassed.
Altera Corporation
October 2007
2–75
Stratix II GX Device Handbook, Volume 1