EP2SGX30CF780C5N Datasheet, PDF (76/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

MultiTrack Interconnect
C16 column interconnects span a length of 16 LABs and provide the
fastest resource for long column connections between LABs, TriMatrix
memory blocks, DSP blocks, and IOEs. C16 interconnects can cross
M-RAM blocks and also drive to row and column interconnects at every
fourth LAB. C16 interconnects drive LAB local interconnects via C4 and
R4 interconnects and do not drive LAB local interconnects directly. All
embedded blocks communicate with the logic array similar to
LAB-to-LAB interfaces. Each block (that is, TriMatrix memory and DSP
blocks) connects to row and column interconnects and has local
interconnect regions driven by row and column interconnects. These
blocks also have direct link interconnects for fast connections to and from
a neighboring LAB. All blocks are fed by the row LAB clocks,
labclk[5..0].
Table 2–18 shows the Stratix II GX device’s routing scheme.
Table 2–18. Stratix II GX Device Routing Scheme (Part 1 of 2)
Destination
Source
Shared arithmetic chain
Carry chain
Register chain
Local interconnect
Direct link interconnect
R4 interconnect
R24 interconnect
C4 interconnect
C16 interconnect
ALM
M512 RAM block
M4K RAM block
M-RAM block
DSP blocks
v
v
v
vvvvvvv
v
v
vvvv
vvvv
v
v
v
vvvv
vvvvvv
v
vvv
v
vvv
v
vvvv
vv
v
2–68
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007