EP2SGX30CF780C5N Datasheet, PDF(43/316 Page) Altera Corporation – Section I. Stratix II GX Device Data Sheet

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EP2SGX30CF780C5N Datasheet, PDF (43/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

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Stratix II GX Architecture

Transceiver Clocking

Each Stratix II GX device transceiver block contains two transmitter PLLs

and four receiver PLLs. These PLLs can be driven by either of the two

reference clocks per transceiver block. These REFCLK signals can drive all

global clocks, transmitter PLL inputs, and all receiver PLL inputs.

Subsequently, the transmitter PLL output can only drive global clock

lines and the receiver PLL reference clock port. Only one of the two

reference clocks in a quad can drive the Inter Quad (I/Q) lines to clock the

PLLs in the other quads.

Figure 2â29 shows the inter-transceiver line connections as well as the

global clock connections for the EP2SGX130 device.

Altera Corporation

October 2007

2â35

Stratix II GX Device Handbook, Volume 1

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