Z16C32 Datasheet, PDF (90/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
IUSC TIMING
PRELIMINARY
Z16C32 IUSC^™
The IUSC interface timing is similar to that found on a static
RAM, except that it is much more flexible. Up to four
separate timing strobe signals are present on the inter-
face: /DS, /RD, /WR and /INTACK. Only one of these timing
strobes is active at any time. Should the external logic
activate more than one of these strobes at the same time,
the IUSC will enter a pre-reset state. This state is only
exited by a hardware reset. Do not allow overlap of timing
strobes. The timing diagrams, beginning on the next page,
illustrate the different bus transactions possible with the
necessary setup, hold, and delay times. IUSC Timing
diagrams are shown from Figure 82 through Figure 106.
DC CHARACTERISTICS
Symbol Parameter
Min
Typ
Max
V
Input High Voltage
2.2
IH
V_IL
Input Low Voltage
–0.3
V
Output High Voltage
2.4
OH1
V +0.3
CC
0.8
V_OH2
Output High Voltage
V_CC –0.8
V
Output Low Voltage
0.4
OL
I_IL
Input Leakage
+10.00
I_OL
Output Leakage
+10.00
I
V Supply Current
7
50
CC1
CC
Note:
V_CC = 5V ± 10% unless otherwise specified, over specified temperature range.
Unit
V
V
V
V
V
µA
µA
mA
Condition
I = –1.6 mA
OH
I_OH = –250 µA
I = +2.0 mA
OL
0.4 < V_IN < +2.4V
0.4 < V_OUT < +2.4V
V = 5V V = 4.8V V = 0.2V
CC
IH
IL
AC CHARACTERISTICS
Timing Diagrams (Figures 82-104)
/RESET
/STB
113
114
115
Figure 82. Reset Timing
/STB
90
112
1
1
Figure 83. Bus Cycle Timing
Note:
/STB is any of the following: /DS, /RD, /WR or Pulsed /INTACK.
PS97USC0200