Z16C32 Datasheet, PDF (19/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
Z16C32 IUSC^™
Any Transaction
Up To and Including
BCR Write
No /AS
Reset
At Least One /AS
BCR
Write
Transaction
BCR[2]=0
BCR[15]=1
Non-
Multiplexed
Bus
BCR[2]=0
BCR[15]=0
BCR[2]=1
Multiplexed
Bus
BCR[2]=0 BCR[2]=0 BCR[2]=1
BCR[15]=1 BCR[15]=0
8-Bit With
Separate
Address
8-Bit Without
Separate
Address
16-Bit
8-Bit With
Separate
Address
8-Bit Without
Separate
Address
Note:
The presence of one transaction with an /AS active between reset, up to
and including the BCR write, chooses a multiplexed type of bus.
Figure 6. BCR Reset Sequence and Bit Assignments
16-Bit
PS97USC0200
19