Z16C32 Datasheet, PDF (24/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
CONTROL REGISTERS (Continued)
Address: 00001
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Z16C32 IUSC^™
00
01
10
11
Increment
Decrement
Fixed Address
Reserved
Address Mode
0 0 Auto Modes Disabled
0 1 Buffered
1 0 Array Chained
1 1 Linked-Array Chained
DMA Mode
Software Abort (RO)
Hardware Abort (RO)
End of Buffer (RO)
End of Array/Link (RO)
Initialization (RO)
Busy (RO)
Get Link (RO)
Continue (RO)
8-Bit Operand
Enable Early Termination
Ring Buffer Enable
Linked Frame Status Transfer
Figure 9. Tx/Rx DMA Mode Register (TDMR) (RDMR)
24
PS97USC0200