Z16C32 Datasheet, PDF (2/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
GENERAL DESCRIPTION (Continued)
Z16C32 IUSC^™
There are additional reasons for using the Z16C32 IUSC
than just reduced chip count and board space economy.
The DMA and serial channel intercommunication offers
application benefits as well. For example, events such as
the reception of the end of a HDLC frame is internally
communicated from the serial controller to the DMA so that
each frame can be written into a separate memory buffer.
The buffer chaining capabilities, ring buffer support, auto-
mated frame status/control blocks, and buffer termination
at the end of the frame combine to significantly reduce
CPU overhead (Figure 1).
The IUSC is software configurable to satisfy a wide variety
of serial communication applications. The 20 Mbit/second
data rate and multiple protocol support make it ideal for
applications in today’s dynamic environment of changing
specifications and increasing speed. The many program-
mable features allow the user to tune the device response
to meet system requirements and adapt to future require-
ments. The IUSC contains a variety of sophisticated inter-
nal functions including two baud rate generators, a digital
phase-locked loop, character counters, and 32-byte FIFOs
for both the receiver and the transmitter.
data without separate address to support multiplexed or
non-multiplexed busses.
The IUSC handles asynchronous formats, synchronous
bit-oriented formats such as HDLC and synchronous byte-
oriented formats (e.g., BISYNC and DDCMP). This device
supports virtually any serial data transfer application.
The IUSC can generate and check CRC in any synchro-
nous mode. Complete access to the CRC value allows
system software to resend or manipulate the CRC as
needed in various applications. The IUSC also provides
facilities for modem control signals. In applications where
these controls are not needed, the modem controls can be
used for general-purpose I/O.
Interrupts are supported by a daisy-chain hierarchy within
the serial channel and between the serial channel and the
DMA. Separate interrupt vectors for each type of interrupt
within the serial controller and the DMA facilitate fast
discrimination of the interrupt source. The IUSC supports
Pulsed, Double Pulsed, and Status Interrupt Acknowledge
cycles.
The on-chip DMA channels allow high speed data trans-
fers for both the receiver and the transmitter. The IUSC
supports automatic status and control transfer through
DMA and allows initialization of the serial controller under
DMA control. Each DMA channel can do a 16-bit transfer
in as little as three 50 ns clock cycles and can generate
addresses compatible with 32-, 24- or 16-bit memory
ranges. The DMA channels operate in any of four modes:
single buffer, pipelined, array-chained, or linked-list. The
array-chained and linked-list modes provide scatter-read
and gather-write capabilities with minimal software inter-
vention. To prevent the DMA from holding bus mastership
too long, mastership time may be limited by counting the
absolute number of clock cycles, the number of bus
transactions, or both.
The CPU bus interface is designed for use with any
conventional multiplexed or non-multiplexed bus from
manufacturers of CISC and RISC processors including
Intel, Motorola, and Zilog. The bus interface is configurable
for 16-bit data, 8-bit data with separate address or 8-bit
Support tools are available to aid the designer in efficiently
programming the IUSC. The Technical Manual describes
in detail all the features and gives programming sequence
hints. The Electronic Programmer's Manual, DC #8287-02,
is an MS-DOS, disk-based programming initialization tool
that can generate custom sequences. Also, Zilog offers
assorted application notes and development boards to
assist the designer in hardware and software develop-
ment. Contact your nearest Zilog representative for addi-
tional information.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
V_CC
V_DD
Ground
GND
V_SS
2
PS97USC0200