Z16C32 Datasheet, PDF (61/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
Address: 01000
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Z16C32 IUSC^™
0 0 0 Disabled
0 0 1 /RxC Pin
0 1 0 /TxC Pin
0 1 1 DPLL Output
1 0 0 BRG0 Output
1 0 1 BRG1 Output
1 1 0 CTR0 Output
1 1 1 CTR1 Output
Receive Clock
Source
0 0 0 Disabled
0 0 1 /RxC Pin
0 1 0 /TxC Pin
0 1 1 DPLL Output
1 0 0 BRG0 Output
1 0 1 BRG1 Output
1 1 0 CTR0 Output
1 1 1 CTR1 Output
Transmit Clock
Source
0 0 BRG0 Output
0 1 BRG1 Output
1 0 /RxC Pin
1 1 /TxC Pin
DPLL Clock
Source
0 0 CTR0 Output
0 1 CTR1 Output
1 0 /RxC Pin
1 1 /TxC Pin
BRG0 Clock
Source
0 0 CTR0 Output
0 1 CTR1 Output
1 0 /RxC Pin
1 1 /TxC Pin
BRG1 Clock
Source
0 0 Disabled
0 1 Port0 Pin
1 0 /RxC Pin
1 1 /TxC Pin
CTR0 Clock
Source
0 0 Disabled
0 1 Port1 Pin
1 0 /RxC Pin
1 1 /TxC Pin
CTR1 Clock
Source
Figure 54. Clock Mode Control Register (CMCR)
PS97USC0200
61