Z16C32 Datasheet, PDF (39/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
Z16C32 IUSC^™
Base Address
Base Address + 1
Base Address + 2
Base Address + 3
Base Address + 4
Base Address + 5
Base Address + 6
Base Address + 7
Base Address + 8
Base Address + 9
Base Address + 10
Base Address + 11
Base Address + 12
Base Address + 13
Base Address + 14
Base Address + 15
Base Address + 16
Base Address + 17
Base Address + 18
Base Address + 19
Base Address + 20
Base Address + 21
Base Address + 22
Base Address + 23
Buffer #1
Buffer #2
AD7
AD0
AD<31-24>
AD<23-16>
AD<15-8>
AD<7-0>
CNT<15-8>
CNT<7-0>
RSB/TCB <15-8>
RSB/TCB <7-0>
RCHR/TCLR <15-8>
RSHR/TCLR <7-0>
0
0
AD<31-24>
AD<23-16>
AD<15-8>
AD<7-0>
CNT<15-8>
CNT<7-0>
RSB/TCB <15-8>
RSB/TCB <7-0>
RCHR/TCLR <15-8>
RSHR/TCLR <7-0>
0
0
Last Base Address
Last Base Address + 1
Last Base Address + 2
Last Base Address + 3
Last Base Address + 4
Last Base Address + 5
Base Address Register
After Termination
Dummy
Ignored
Ignored
Ignored
Ignored
00000000
00000000
Figure 28b. Array-Chained, 8-Bit Bus, Big End Array,
Linked Frame Status Transfer Enabled
PS97USC0200
39