Z16C32 Datasheet, PDF (115/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
Z16C32 IUSC^™
No
Symbol
Parameter
Min
Max Units Note
147
TdCLK(ADz)
148
TdCLK(ADa)
149
TsAD(UAS)
150
ThAD(UAS)
CLK Rise to Address Float Delay
CLK Rise to Address Active Delay
Address to /UAS Rise Setup Time
Address to /UAS Rise Hold Time
35
ns
[6]
35
ns
[6]
10
ns
[6]
10
ns
[6]
151
TsAD(AS)
Address to /AS Rise Setup Time
10
152
ThAD(AS)
Address to /AS Rise Hold Time
10
153
TsW(CLK)
/WAIT to CLK Fall Setup Time
10
154
ThW(CLK)
/WAIT to CLK Fall Hold Time
15
ns
[6]
ns
[6]
ns
[6]
ns
[6]
155
TsRDY(CLK)
/READY to CLK Fall Setup Time
10
156
ThRDY(CLK)
/READY to CLK Fall Hold Time
15
157
ThDW(CLK)
Write Data to CLK Rise Hold Time
0
158
TdAS(DSw)
/AS Rise to /DS Fall (Write) Delay
40
ns
[6]
ns
[6]
ns
[6]
ns [6,10,13]
159
TsDW(DS)
Write Data to /DS Fall Setup Time
25
160
TwDSlw
/DS (Write) Low Width
45
161
ThDW(DS)
Write Data to /DS Rise Hold Time
25
162
TdAS(WR)
/AS Rise to /WR Fall Delay
40
ns [6,7,13]
ns [6,11,13]
ns
[6,8]
ns [6,10,13]
163
TsDW(WR)
164
TwWRl
165
ThDW(WR)
166
TdCLK(WR)
Write Data to /WR Fall Setup Time
/WR Low Width
Write Data to /WR Rise Hold Time
CLK Fall to /WR Delay
25
ns [6,7,13]
45
ns [6,11,13]
25
ns
[6,8]
30
ns
[6]
167
TdCLK(BUSz)
168
TsABT(CLK)
169
ThABT(CLK)
170
TdCLK(BRQ)
CLK Rise to Bus Float Delay
/ABORT to CLK Rise Setup Time
/ABORT to CLK Rise Hold Time
CLK Rise to /BUSREQ Delay
30
ns
[6]
20
ns
[6]
15
ns
[6]
30
ns
[6]
171
TdCLK(BUSa)
172
TsBIN(CLK)
173
ThBIN(CLK)
174
TsBRQ(CLK)
175
ThBRQ(CLK)
176
TdBIN(BOT)
CLK Rise to Bus Active Delay
/BIN to CLK Rise Setup Time
/BIN to CLK Rise Hold Time
/BUSREQ to CLK Rise Setup Time
/BUSREQ to CLK Rise Hold Time
/BIN to /BOUT Delay
30
ns
[6]
20
ns
[6]
15
ns
[6]
25
ns
[6]
0
ns
[6]
60
ns
Notes:
AC Test Conditions:
V_CC = 5V ± 5% unless otherwise specified,
over specified temperature range.
V_IH = 2.0V V_OH = 2.0V
V_IL = 0.8V V_OL = 0.8V
Float = +0.5V
[1] Direct Address is any of S//D, D//C or AD15-AD8 used
as an address bus.
[2] The parameter applies only when /AS is not present.
[3] Strobe is any of /DS, /RD, /WR or Pulsed /INTACK.
[4] Parameter applies only if read empties the receive FIFO.
[5] Parameter applies only if write fills the transmit FIFO.
[6] Parameter applies only while the IUSC is bus master.
[7] Parameter is clock-cycle dependent, TwCLKh + TfCLK – 5.
[8] Parameter is clock-cycle dependent, TwCLKl + TrCLK –5
[9] Parameter is clock-cycle dependent,
TcCLK + TwCLKh + TfCLK –5.
[10] Parameter is clock-cycle dependent, TcCLK –10.
[11] Parameter is clock-cycle dependent, TcCLK –5.
[12] Clock cycle parameters TwCLKh and TcCLK have unique
values for Linked List Mode. In Linked List Mode, the system clock
cycle is extended to 60 ns, and the system clock High pulse width
is extended to 35 ns. This is due to the internal timing paths unique
to the Linked List Mode. The transmit and receive bit rates are not
affected.
[13] For Linked List Mode, the minimum for these values should be
calculated using TwCLKh = 35 ns and TcCLK = 60 ns.
PS97USC0200
115