Z16C32 Datasheet, PDF (27/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
Z16C32 IUSC^™
Big End Array
(16-Bit bus)
AD15
AD0
Address n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Address n+2 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Little End Array
(16-Bit bus)
AD15
AD0
Address n 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Address n+2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Big End Array
(8-Bit bus)
AD7
AD0
Address n 31 30 29 28 27 26 25 24
Address n+1 23 22 21 20 19 18 17 16
Address n+2 15 14 13 12 11 10 09 08
Address n+3 07 06 05 04 03 02 01 00
Little End Array
(8-Bit bus)
AD7
AD0
Address n 07 06 05 04 03 02 01 00
Address n+1 15 14 13 12 11 10 09 08
Address n+2 23 22 21 20 19 18 17 16
Address n+3 31 30 29 28 27 26 25 24
Figure 12. Array-Chained Bit Ordering
Note:
Bit 12 in DCR is used to control the byte ordering of addresses and counts stored in memory in the
Array and Linked Array Modes. The above figure shows the two cases for both bus bandwidths.
PS97USC0200
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