Z16C32 Datasheet, PDF (25/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
D7 D6 D5 D4
0 0 0 0 Channel Disabled
0 0 1 0 Channel Enabled
X X X 1 Not Possible
X 1 X X Not Possible
1 X X X Not Possible
Initialization
Busy
Get Link
Continue
Normal Mode
Z16C32 IUSC^™
0 0 0 0 Channel Disabled, Base Registers Invalid
0 0 1 0 Channel Enabled, Base Registers Invalid
1 0 0 0 Channel Disabled, Base Registers Valid
1 0 1 0 Channel Enabled, Base Registers Valid
X X X 1 Not Possible
X 1 X X Not Possible
Buffered Mode
0 0 0 0 Channel Disabled, Data Transfer Phase
0 0 1 0 Channel Enabled, Data Transfer Phase
0 0 0 1 Channel Disabled, Array Transfer Phase
0 0 1 1 Channel Enabled, Array Transfer Phase
X 1 X X Not Possible
1 X X X Not Possible
Array-Chained Mode
0 0 0 0 Channel Disabled, Data Transfer Phase
0 0 1 0 Channel Enabled, Data Transfer Phase
0 0 0 1 Channel Disabled, Array Transfer Phase
0 0 1 1 Channel Enabled, Array Transfer Phase
0 1 X 0 Not Possible
0 1 0 1 Channel Disabled, Link Transfer Phase
0 1 1 1 Channel Enabled, Link Transfer Phase
1 X X X Not Possible
Linked Array-Chained Mode
Figure 10. Status Bit Combinations
PS97USC0200
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