Z16C32 Datasheet, PDF(62/121 Page) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

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Z16C32 Datasheet, PDF (62/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

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ZILOG

PRELIMINARY

CONTROL REGISTERS (Continued)

Address: 01001

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 0 Disabled

0 1 NRZ/NRZI

1 0 Biphase-Mark/Space

1 1 Biphase-Level

DPLL

Divider

0 0 32x Clock Mode

0 1 16x Clock Mode

1 0 8x Clock Mode

1 1 Reserved

DPLL Clock

Divider

0 0 32x Clock Mode

0 1 16x Clock Mode

1 0 8x Clock Mode

1 1 4x Clock Mode

CTR0 Clock

Divider

Z16C32 IUSCâ¢

BRG0 Enable

BRG0 Single Cycle/Continuous

Reserved

BRG1 Enable

BRG1 Single Cycle/Continuous

Reserved

Code Violations OK

CTR1 Rate Match DPLL/CTR0

Figure 55. Hardware Configuration Register (HCR)

62

PS97USC0200

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