Z16C32 Datasheet, PDF (44/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
CONTROL REGISTERS (Continued)
Base Address
Base Address + 1
Base Address + 2
Base Address + 3
Base Address + 4
Base Address + 5
AD7
AD0
Buffer #1
AD<7-0>
AD<15-8>
AD<23-16>
AD<31-24>
CNT<7-0>
CNT<15-8>
Base Address + 6
Base Address + 7
Base Address + 8
Base Address + 9
#2 Base Address
#2 Base Address + 1
#2 Base Address + 2
#2 Base Address + 3
#2 Base Address + 4
#2 Base Address + 5
Base #2
Buffer #2
AD<7-0>
AD<15-8>
AD<23-16>
AD<31-24>
AD<7-0>
AD<15-8>
AD<23-16>
AD<31-24>
CNT<7-0>
CNT<15-8>
#2 Base Address + 6
#2 Base Address + 7
#2 Base Address + 8
#2 Base Address + 9
Base #3
AD<7-0>
AD<15-8>
AD<23-16>
AD<31-24>
Figure 32a. Linked Array-Chained, 8-Bit Bus, Big End Array
Note:
The addition of frame status/control information in the array with Linked
Frame Status Transfer Enabled is similar to Big End Array. See Figure 32b.
Z16C32 IUSC^™
44
PS97USC0200